The nanometre number on a chip stopped being a measurement

This is written to be used rather than admired. Each section below is a decision about semiconductor process nodes, and each one has a default.

It used to mean something specific

For decades the node name referred to a real physical dimension, roughly the smallest gate length that could be printed. Each generation shrank that dimension, which increased density, reduced switching energy and increased speed together. That neat relationship broke when transistors stopped being flat and became three-dimensional structures with fins and then stacked sheets.

Once the geometry changed, no single length described the generation, but the naming convention survived because customers understood it.

What replaced it

Foundries now name nodes to indicate a generation and its approximate competitive position rather than a dimension. The result is that processes from different manufacturers sharing a number can differ substantially in density and efficiency.

Under load, some vendors have shifted to angstrom-based names, which changes the unit rather than the underlying looseness. Industry bodies have proposed density-based metrics for years without achieving consistent adoption.

Density is the number that matters

Transistors per square millimetre determines how much logic fits in a given area, which is what a chip designer is actually buying. Density varies within a single chip because memory arrays pack far more tightly than logic does, so a single figure is already an approximation. Manufacturers publish density figures selectively, which makes independent comparison difficult and estimates common.

When a comparison quotes only node names it is comparing labels rather than processes.

Shrinking no longer delivers what it did

Historically each node reduced power per operation enough that more transistors could all be active at once. That scaling relationship weakened, which is why chips now contain far more transistors than can be powered simultaneously at full speed. The response has been specialised blocks that sit idle until needed, which is why modern chips contain many accelerators rather than more general cores.

Cost per transistor has also stopped falling reliably, which changes the economics that drove the whole industry.

Packaging became the other half

Stacking separate pieces of silicon and connecting them densely delivers gains that no longer come from shrinkage alone. Splitting a design into chiplets improves manufacturing yield, because a defect ruins a small piece rather than a large one.

The short version: these advances are invisible in node naming, which is one reason node naming has become a poor summary of a product. Memory placed close to logic reduces the energy spent moving data, which is now a larger share of total consumption than computation in many workloads.

Firmware updates change this behaviour more often than hardware does.

How to read a chip announcement

Treat the node name as a generation label and look instead for stated improvements in performance at equal power, or power at equal performance. Those paired figures are the honest form and vendors that supply them are describing something checkable. A claim of a percentage improvement with no stated baseline condition is not a measurement.

For a buyer, the behaviour of the finished device under sustained load settles more than any process discussion.

The takeaway

Read the node name as a generation, not a dimension. The density and the power figures are the real content.

The constraint is almost always physical, and marketing rarely mentions which one.